Multi-Level Error Detection Scheme Based on Conditional DIVA-Style Verification

As a processor gets smaller and faster, it becomes more sensitive to both the increasing process variation and environment disturbances such as cosmic rays and heat. These imperfections and uncertainties lead to transient errors or even destructive malfunctions of the processor. The previous effort on processor execution error detection includes the DIVA scheme [1], which excels other dynamic verification schemes in its simplicity and high error coverage. However, the high degree of execution redundancy leads to considerable performance overhead and hardware / power cost. Aiming to enhance the verification efficiency in DIVA-like dynamic schemes, this paper presents a Multi-level Error Detection Scheme (MEDS) based on conditional DIVA-style verification. In this architecture the program instruction stream is filtered by an error indicator before entering DIVA checking stage. Experiments on the SimpleScalar simulator demonstrate that by applying effective error indicators, the instruction re-execution costs can be significantly reduced at a small error-missing rate penalty. The design tradeoffs between error coverage and verification efficiency is analyzed through the experiments on applying different reorder buffer overflow handling schemes and checker processor bandwidths. Finally, future improvements to further enhance the efficiency of MEDS are suggested.